APA

Sharma S., Sharma D. e. & Sharma V. j. e. (2017). Digital elecronics and logic design for (B.E. , BTech, B.Sc (E(Engineering), A.M.I. E. (India), A.M.I.E.E. (London), Grad I.E.T.E. (India), GATE, UPSC. , I.E.S. , and other various Engg. & Competitive examinations) / Sanjay Sharma. New Delhi: S.K. Katarina & Sons.

Chicago

Sharma Sanjay, Sharma Deeksha ed and Sharma V jt ed. 2017. Digital elecronics and logic design for (B.E. , BTech, B.Sc (E(Engineering), A.M.I. E. (India), A.M.I.E.E. (London), Grad I.E.T.E. (India), GATE, UPSC. , I.E.S. , and other various Engg. & Competitive examinations) / Sanjay Sharma. New Delhi: S.K. Katarina & Sons.

Harvard

Sharma S., Sharma D. e. and Sharma V. j. e. (2017). Digital elecronics and logic design for (B.E. , BTech, B.Sc (E(Engineering), A.M.I. E. (India), A.M.I.E.E. (London), Grad I.E.T.E. (India), GATE, UPSC. , I.E.S. , and other various Engg. & Competitive examinations) / Sanjay Sharma. New Delhi: S.K. Katarina & Sons.

MLA

Sharma Sanjay, Sharma Deeksha ed and Sharma V jt ed. Digital elecronics and logic design for (B.E. , BTech, B.Sc (E(Engineering), A.M.I. E. (India), A.M.I.E.E. (London), Grad I.E.T.E. (India), GATE, UPSC. , I.E.S. , and other various Engg. & Competitive examinations) / Sanjay Sharma. New Delhi: S.K. Katarina & Sons. 2017.